The design of LDPC decoder based on FPGA Programming in C

A new design approach of the LDPC decoder based on FPGA Impulse C Programming is proposed. The latest technique of Impulse C programming is used to implement hardware circuit, which is more efficient than the traditional HDL method. The decoder for a family of (3,6) LDPC Codes with 0.5 code rate and the block size of 2500 bits is implemented on Xilinx Virtex2 XC2V2000. When the maximum iteration time is 10 and the frequency is clocked at 50MHz, the throughput is 10 Mbps.