High speed comparator for flash ADC and UWB application in 130 nm CMOS technology

High speed comparator for high-speed flash analog-to-digital converter (ADC) and ultra wideband applications that can work at a sampling rate of 7 GS/s is presented in this paper. This fully differential comparator consists of three stages using a new structure to improve its performance. The offset voltage of the designed comparator has been reduced by means of an active positive feedback. The analyses and simulation results were obtained by using 130 nm CMOS parameters. The comparator can operate with a 1 V peak-to-peak input range consuming 371 µW. The predicted performance is verified by analyses and simulations using HSPICE tool.