Concept and Development of Modular VLIW Processor Based on FPGA

Modern FPGA chips, with their larger memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high density FPGAs it is now possible to implement a high performance VLIW processor core in an FPGA. Architecture based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance level in embedded system. In VLIW architecture, the effectiveness of these processors depends on the ability of compilers to provide sufficient instruction level parallelism(ILP) in program code. Using advanced compiler technology could take these functions, This paper describes research result about enabling the DSP TMS320 C6201 model that be described with machine description language (MDES) in compiler technology for image processing applications by exploiting FPGA technology and assembly code that be more known as Lcode would be generated by the compiler depends on MDES given when running the compiler. We present a DSP C6201 VHDL from MDES definition with VLIW architecture model using compiler technology. We call this new development as Modified Minimum Mandatory Modules (M4) approach that be derived from M3 methodology. Our goals are to keep the flexibility of DSP in order to shorten the development cycle. Our results demonstrate that an algorithm can easily, in an optimal manner, specified and then converted to VHDL language and implemented on an FPGA device with system level software. This makes our approach suitable for developing co-design environments. Our approach applies some criteria for co-design tools : flexibility modularity, performance, and reusability.