A 0.8μm CMOS Programmable Analog-Array-Processing Vision-Chip with Local Logic and Image-Memory

An operational vision-chip prototype with a wide-range of potential applications in artificial-vision systems is presented. Its functionality includes concurrent image-transduction, programmable image-processing, image-storage, and algorithmic control over a network of 20 × 22 identical cells. The prototype has been designed and manufactured in 0.8μm CMOS standard technology, and has a total area of 30mm². Experimental results are reported.