Low Power Logic for Micron and sub-Micron Bipolar Processes

The first attempt at an improved logic form was reported in reference 1. The circuit diagram is shown in figure 1. The chief attribute of this circuit is the use of a junction FET in place of a PNP transistor in an "I2L" - like configuration. This was first demonstrated on a 3-micron fast digital process which did not offer a PNP, but where it was desirable to have high packing density logic. Since this process featured "walled" emitters, it was a relatively easy task to provide an FET by running the emitter implant straight across a p-type resistor. This generates a device which could equally well be described as an FET or as a "pinch" resistor. Although not particularly fast on this process, due to the very low current and the saturation of the NPN transistor in the "on" state, very good power-delay products were recorded for the ring oscillators. This style of gate will be mentioned below in the context of the new process trials. With the advent of a 1-micron based bipolar technology, the requirement for a power efficient logic became more obvious, since the process has a capability for at least 20,000 gates per chip. It would in most cases be impractical on power dissipation grounds to run all these gates at full speed if there was no requirement in the circuit to do so.