CORDIC Processor with Carry-Save Architecture

A CORDIC processor for vector rotations using a carry-save architecture has been developed and realized. The CORDIC algorithm is based on an iteration, directed by the sign of intermediate results. To achieve a high clock frequency of 60 MHz the CORDIC iteration was built up with pipelined carry-save adder stages. Due to the redundant number representation of the carry-save architecture an exact sign detection is not possible, so that the algorithm had been modified. Due to the high throughput rate and its regularity this architecture is well suited for real-time applications.