A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDR

This paper presents the design of a 14 bit, 280 kS/s cyclic ADC which consumes 1.6 mW power and achieves 100 dB SFDR. The design is optimized with a half-scale residue transfer characteristic (RTC) which lowers swing and slew requirements on the opamp. Further advantages of this RTC are exploited to reduce the number and magnitude of dominant error sources, and the residual error is randomized with dithering. Capacitor scaling and optimized allocation of conversion time to each step add to power savings. The ADC fabricated in a 0.35 ¿m CMOS process occupies 1.04 mm² silicon area.