A multilevel multilayer partitioning algorithm for three dimensional integrated circuits

In this paper, we propose a multilevel multilayer partitioning algorithm for 3D ICs application. The algorithm is based on the multilevel framework to coarsen the netlist successively. A multilayer partitioning procedure is applied on each level of partition during the un-coarsening process. The objective is to minimize the total number of Through Silicon Via (TSV) while observing the area constraint for each layer. The area of each layer is the summation of circuit area and TSV area. The partitioning algorithm is customized for the structure of 3D ICs. We utilize a FM-like data structure and identify eight critical net distributions such that after a cell move, the program can update gains very effectively. The experimental results show that the proposed algorithm can effectively produce good results with small numbers of TSV, area overhead, and area coefficient of variation for the tested industrial cases. The average area overhead is only 1.84% that shows the average white space is very small. The average area coefficient of variation is only 2.61% that shows area distribution of all layers is very uniform. The results also achieve the best average value for both number of TSVs and chip area, compared to all participating teams in “Design Partition for 3D ICs” problem in the IC/CAD 2009 contest in Taiwan.