CIT 1 and CIT 2, Advanced Non Epitaxial Bipolar/CMOS Processes for Analog-Digital VLSI

Deux processus Bipolaire/CMOS de haute performance ont ete developpes; les processus CIT 1 (2.0 μm) et CIT 2 (1.5 μm). La technologie CIT n'utilise ni l'epitaxie ni le buried layer. Des transistors bipolaires (npn, pnp) et des transistors MOS (canal n, canal p) sont implantes avec succes sur un meme chip sans diminuer les performances des deux technologies en présence. Two N-well high performance Bipolar/CMOS processes have been developed; a 2.0 μm CIT 1 process and CIT 2, a 1.5 μm process. CIT technology uses neither epitaxie nor buried layer. Bipolar transistors (npn and pnp) and MOS transistors (n-channel and p-channel) have been sucessfully fabricated on the same chip without a decrease of the performance.