Well Technologies for Half-micron CMOS Processes

Scaling CMOS processes to sub-μm dimensions requires a reduction of lateral well extensions to be able to shrink the n⁺-p⁺ spacing. This paper describes concepts for reducing the lateral extension of n-wells on p-substrate. Three well types have been compared: (1) a deep n-well fabricated by long drive-in, (2) a shallow n-well made by very short drive-in, (3) an n-well superimposed on the p-well by counter doping the p-well in the n-well areas. Whereas device performance of thin oxide PMOSFETs is identical for all three wells, considerable difference has been observed for lateral well isolation and latchup.