High Performance 0.3 μm CMOS Technology using I-Line Lithography

A 0.3 μn CMOS process with an advanced LOCOS field isolation in combination with optimized I-line photolithography is described. High device performance maintaining low off-state leakage currents were obtained using retrograde well technology in combination with shallow junction drain extension devices. The key process technology is the improved poly linewidth control through the use of BARC without degrading device performance.