A bitline sense amplifier for offset compensation

The industry has continuously demanded lower voltages and higher densities in DRAM chips [1]. To satisfy this need, it is desirable to use a low V
CORE
in the DRAM core, even though with such a low voltage it is difficult to sense the cell signal due to an insufficient sensing margin in high density DRAM [2–3]. When the bitline (BL) sense amp (BLSA) starts the sensing operation, all the BLs in the cell array go to the data transition stage. This leads to sensing noise in the BLSA, resulting in a sensing failure. There are several noise sources that contribute to this sensing failure, but the major noise source is the coupling capacitance between the BL and the wordline (WL) [4], which leads to a cell MAT array noise as shown by the data patterns. We develop a BLSA to compensate for this MAT sensing noise. In this experiment, we fabricate a 68nm DRAM chip that shows only a 15% amplitude of the total normal chip noise by eliminating 85% of original MAT sensing noise by using a new BLSA scheme. Fabricated DRAM chips operate in the condition of V
CORE
= 1.5V and V
DD
= 1.8V. Generally, a sensing margin problem occurs in BLSAs with a large threshold voltage mismatch. Because this kind of worst-case BLSA is rare, we focus only on the worst BLSA found with a probability of 10
⁻³
%. All the measured data is from the BLSAs of 10
⁻³
% probability, which we define as a sensing margin failure.