Session 26 overview: High-performance & digital PLLs

Phase-locked loops (PLLs) are an essential component in many wireline and wireless applications for clocking and frequency synthesis. The relentless increase in system complexity coupled with process scaling calls for new techniques for low-noise and low-spur performance. This session presents eight papers that explore innovations in all-digital and sub-sampling PLLs. A common theme in all digital PLLs is to improve the linearity and resolution of the time-to-digital converter (TDC). Seven of the eight papers in this session address this issue.