Dependence of program and erase speed on bias conditions for fully depleted channel of vertical NAND flash memory devices

Recently, various kinds of novel flash memory devices have been incessantly developed. Especially, a number of devices in vertical structures have been proposed for higher integration. In many cases, the silicon channels are constructed in a vertical manner so that the memory cells share a common channel. For the sake of higher integration density, thickness of silicon channel should be essentially thin, which makes fully depleted channels usually. There have been reports concerned with the effects of channel depletion states on read current in vertical flash memory devices, but those of program/erase operations have seldom been reported. In this work, the program/erase speeds with regard to channel thickness (TSi), bias conditions on the paired cell are investigated by device simulation.