Multiscale modeling for reliability assessment in microelectronic systems

In this paper, we discuss challenges to modeling reliability in microelectronic systems wherein issues generically involve evolving heterogeneities such as cracks, voids, and secondary phases occur across all relevant length scales starting from the circuit board down to the Inter-Layer Dielectric (ILD). Increasingly the failures at ILD lengthscales are driven by package construction or material choices such as the underfill stiffness. Thus, often, a complex combination of material, geometry, and loading together determine whether local (such as a specific ILD layer or via location) or global (such as a package solder balls or underfill) failures occur preferentially. In this paper we describe several examples of reliability modeling from our recent research spanning both the package-level and die-level reliability issues.