Design issues and possible solutions for low-cost and high-efficiency LSIs

Large scale integration with advanced CMOS technologies has been reducing cost, but maintaining chip dependability is becoming more and more difficult. This is due to increasing complexity of system design and increasing uncertainty of signal timing and level. Chip dependability can be realized at low cost and maintain high efficiency by combining technologies of (A) “Never produce defects” during chip design and manufacturing, (B) “Never let defects escape” during chip testing, and (C) “Never let defects lead to failure” during operations, as shown in Fig. 1.