Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization

A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO
₂
based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and T
_inv
values of ˜5 Å and ˜8 Å respectively for both n and pMOS devices. The drive currents at I
_off
=100 nA/μm with V
_DD
=1 V is 1.4 mA/μm and 0.6 mA/μm (no SiGe source/drain) for n and pMOS respectively. The technology further offers low n/pMOS V
_T
of 0.3/-0.4V, good V
_T
-uniformity, and V
_T
-matching and very high cutoff frequencies at ˜290-340 GHz for 38 nm nMOS devices. A replacement poly gate process is used to further improve upon the pMOS effective work function. TDDB lifetimes over 10 years are reported while BTI indicates potential reliability challenges.