Potential well engineering by partial oxidation of TiN for high-speed and low-voltage Flash memory with good 125°C data retention and excellent endurance

Potential well engineering is proposed for NAND Flash memory. With a variable (~2nm-4.3nm) tunnel barrier, the engineered well (EW) enhances tunneling of carriers during program/erase (P/E) to result in fast P/E, while it suppresses charge loss under the retention mode to result in good data retention. The EW also improves endurance, as it is insensitive to the P/E stress induced tunnel barrier degradation. The EW demonstrated in this work is formed by partial oxidation of TiN at the interfaces of the SiO
₂
/TiN/SiO
₂
stack during rapid thermal process (RTP), and its band profile is characterized by XPS, TEM, internal photoemission (IPE), XRD, and band simulation. The memory devices with an EW show promising performances in fast program (< ¿s), low-voltage operation (6-8 MV/cm), good 10-year data retention at 125°C, and excellent endurance (> 10
⁷
P/E cycles).