Pipeline power reduction through single comparator-based clock gating

Enable-based Clock Gating (ECG) during synthesis to reduce the pipeline power consumption is widely used in scaled technologies. However, the ECG does not provide optimal solution at all in terms of power because it is synthesized by a global way and it does not consider the correlation between clock-enable signal and data signal. We propose a novel single comparator-based clock gating (SCCG) scheme to enhance the ECG for pipeline. In the proposed SCCG, enable signal is moved from data path to control logic, the data signal is analyzed, and only single comparator is used to implement the clock-gating for all the pipeline stages. Simulation results show that our proposed SCCG can save average 47.03% of total power with small 4-stage pipeline benchmark and can save 11.3% of total power with industrial multimedia-mobile processor design by using 90 nm industrial technology library comparing with the ECG-based designs.