DFT for achieving hybrid transiton delay fault test with Reduced Pin Count Testing

This paper presents a new DFT (design-for-testability) for achieving the hybrid TDF (transition delay fault) test with RPCT (reduced pin count testing). RPCT can perform stuck-at test only due to the limitation of boundary scan structure. With increasing of operating frequency, it is more important to perform at-speed tests and achieve higher TDF coverage. With our proposed design, it is possible to perform at-speed delay test in RPCT structure with little hardware overhead and higher test throughput. Experimental results for ISCAS89 and ITC99 benchmark circuits prove that the proposed design is effective for the test cost reduction by minimizing hardware overhead and maximizing multi-site test.