Pre-layout performance prediction for automatic macro-cell synthesis

In this paper we present an approach allowing the area and delay prediction of macro-cells to be used in automatic layout synthesis tools. These parameters are of great importance in IC design. They allow us to guide the floor planning phase of an IC by specifying the number of rows and the aspect ratio of the macro-cell or to explore the power delay trade-off by selecting the size of the transistors (before layout generation) to satisfy the user constraints. We propose here a calibration method based on specific benchmarks to determine post-layout parasitic contribution at pre-layout level. Experimental results are given when we compare predicted and simulated post-layout performances of various circuits for different sizing alternatives.