Design of synchronous parallel controllers for low-power applications

Transition signalling is a convention whereby any signal transition has the same meaning and is interpreted as an event. Such a conceptual framework is particularly well suited to asynchronous circuit design, where it has been successfully employed. This paper investigates how transition signalling can be used in the design of synchronous parallel controllers to reduce power consumption. Experimental results of controller implementation are encouraging, especially for highly parallel systems, where significant power savings can be achieved. Double-edge-triggered (DET) flip-flops, which provide a power-efficient solution to the realization of data registers, can easily be interfaced with synchronous controllers based on transition signalling. This makes the new approach a very attractive option for low-power system design.