DC-current-free low-power A/D converter circuitry using dynamic latch comparators with divided-capacitance voltage reference

We have developed a new A/D converter architecture by applying the concept of clocked-neuron-MOS circuitry. It features no DC power dissipation at any component in the A/D converter. In this architecture a comparator employs dynamic latch and the reference voltage is generated by a capacitive voltage divider configuration. As a result, all components in the A/D converter have become purely dynamic in their operation, resulting in a dramatic reduction in the power dissipation. These techniques have been combined with a flash and a two-step flash mechanism, and extremely-low-power A/D converters have been developed. Test circuits were fabricated using standard double-polysilicon CMOS process with 3 /spl mu/m rules. The basic performance has been confirmed by the measurement of test circuits as well as by HSPICE simulation.