Clock skew on DRAM/logic merged technology based systems

This paper describes the clock skew estimations considering all the possible clock skew factors on DRAM/Logic merged systems. The clock skew difference between a standard logic chip and DRAM/Logic merged chips has been estimated as 521 ps for 4/spl times/4 cm/sup 2/ die size. The relationship between clock skew and die size on DRAM/Logic merged systems has been obtained along with the maximum operating clock frequency assuming clock skew can take up to 15% of the total clock cycle on such a large chip.