A resonant signal driver for two-phase, almost-non-overlapping clocks

We describe a driver circuit for reducing the power dissipated when driving heavily loaded signals such as the clock lines of a VLSI chip. The design exhibits good power efficiency across a wide range of frequencies. We have tested the driver with a prototype shift-register chip which had a clock line load in the hundreds of picofarads. The worst-case overall dissipation was 35% of fCV/sup 2/ at 13 MHz and 5 V.