Influence of machine model ESD stress on the failure thresholds of CMOS protection circuit elements

Machine Model (MM) failure thresholds have been investigated in CMOS protection circuit elements: both N-type and P-type devices of diode, punchthrough, Thick Field Oxide (TFO) transistor, and bulk transistor structures including the electro-thermal simulation and the characterization of Electro-Static Discharge (ESD) induced damage. This paper reports the interaction between electrical and thermal behaviors in CMOS input protection circuit simulations during MM ESD stress. Some observation are described as unique features in the MM ESD device characterization. For a channel length dependency, the MM ESD threshold failure voltage (V/sub esd/) has bell-shaped curve for bulk transistors as well as almost constant value for TFO transistors.