A 3 V fully integrated digital FM demodulator based on a CMOS pulse-shrinking delay line

A fully digital, low-power FM demodulator circuit is presented. The function of the demodulator is based on measuring the cycle time of hard-limited IF signal with subnanosecond resolution which is achieved by combining a 20 MHz counter with a 64 tap voltage-controlled pulse shrinking delay line interpolator. The main features of this new detector are a very stable demodulation gain and low and known distortion. The demodulator is implemented in a 0.8 /spl mu/m CMOS process and tested in a mobile telephone environment with external limiting amplifier and D/A converter at an IF frequency of 455 kHz and maximum deviation of 4-8 kHz. Test results showed a performance of SNR over 45 dB and SINAD of 40 dB. The demodulator consumes about 1 mA from a single 3 V supply.