A 3.5 ns, 64 bit, carry-lookahead adder

A 3.5 ns, 64 bit, carry-lookahead adder has been designed in full-custom domino logic and manufactured in a standard 1 /spl mu/m CMOS technology featuring two metal levels. The adder has a novel array structure which represents a variant of the architecture suggested by Brent and Kung. As opposed to the latter, however, it does not require the back propagation of the signals which is necessary for the intermediate carry bits; hence only log/sub 2/ n logic levels are employed for the generation of all the carry signals. Furthermore, the structure is highly regular and modular and can be assembled with n log/sub 2/ n identical cells with a fan-out of 2. Therefore, a compact circuit is achieved with excellent performance. The occupied area is 3370/spl times/482 /spl mu/m/sup 2/ with a worst-case 650 mW power dissipation at 100 MHz.