A unified synapse-neuron building block for hybrid VLSI neural networks

This paper presents a hybrid VLSI technique for implementation of multi-layer neural networks using a unified synapse-neuron building block. A new building block is proposed by integrating a partial S-shape neural nonlinearity within a Multiplying DAC. Circuit techniques are used to generate S-shape neural function from the combination of quadratic characteristics of four MOS devices. The proposed architecture offers design modularity and scalability, silicon area efficiency, reduced interconnection problem and increased robustness.