Design and analysis of wave-pipelined LDPC decoder

This paper presents a novel architecture for LDPC codes using wave pipelining technique. LDPC approaches the near Shannon limit and it was analyzed using sum-product algorithm. Wave pipelining technique overcomes the drawbacks of conventional pipelining, namely latency overhead and area overhead. The proposed architecture is designed with different stages of pipelining and the performance is compared with that of wave pipelined architecture. Synthesis report proves that the wave pipelined architecture reduces the area overhead and latency overhead. As an extension of the work, the multiplier module is analysed with floating point representation. LDPC codes find its applications in WLAN (IEEE 802.11n) and MIMO OFDM.