Efficient mapping on FPGA of convolution computation based on combined CSA-CPA accumulator

In this paper we present some architectures to deal with fast convolution computation based on carry save adders which are intended to be specifically implemented on FPGAs. Carry-save adders are not frequent in FPGA implementations since FPGA has a fast carry propagation path. In this paper we prove that it is possible to use carry-save arithmetic in a efficient way on FPGA for convolution operation. We make use of the specific structure of the FPGA to design an optimized accumulator which is able to deal with carry-save additions as well as carry-propagate additions using the same hardware. This lead to an efficient combined CSA-CPA architecture with fast computation and optimizing the hardware cost. Experimental results for different word lengths are presented to validate our proposal.