Circuits and system simulations for 100Gb/s optical SCM transmission

The SIAM Medea+ project is developing circuits for 100Gbit/s optical communications for use in the next generation Ethernet backbone network. One promising bandwidth-efficient technology is sub-carrier multiplexing (SCM) where quadrature modulated (QAM) signals on different carrier frequencies are combined and subsequently encoded onto an optical carrier. This transceiver approach capitalizes on the increasing speed of silicon technology to perform more of the signal processing in the electrical domain before converting to light. An advanced 65nm CMOS process on HR-SOI substrate will be evaluated for use in implementing the electrical SCM transmitter and receiver suitable for 100Gbit/s transmission. The authors will present the development of a SCM transceiver link model within AWR's Virtual System Simulation (VSS) environment. This model allows the influence of component performance in the electrical domain, particularly non-linearity and noise, to be assessed with respect to the SCM link performance requirements. The design of critical component building blocks in the 65nm CMOS SOI process such as IQ modulators, power combiners and LNAs for the SCM transceiver will be presented. The performance of these components is then assessed in the system simulation environment to investigate the capabilities of CMOS for next generation optical networking with the SCM architecture.