Design and FPGA implementation of a Viterbi decoder: A case study using SystemVerilog and co-simulation

Design and field programmable gate array (FPGA) implementation of a high-speed Viterbi decoder with a constraint length of 7 and a code rate of ½ is presented here. Based on an Algorithmic State Machine (ASM) flowchart of Viterbi algorithm and by taking advantages of lookup tables and parallelism, this hard-decision decoder has a throughput of 510 Mbps. Its RTL code and self-checking test bench are all written in SystemVerilog. The code is functionally verified in various situations, including several directed test cases and numerous random test cases. It is also verified in the Simulink and ModelSim co-simulation environment. The FPGA implementation results show that its core can run as high as 510 MHz, and has 80.39 ns latency.