Optimized system design for fully integrated fractional-N PLL

In this paper, an optimized method is proposed for the design of fully integrated fractional-N PLL system. The main target is to get relatively small capacitor value for on chip low pass filter while satisfy the system phase noise requirement. The method is implemented in CMMB application whose output frequency of the PLL is from 1.88 to 3.48 GHz. With the VCO tuning gain varying from 50 to 100 MHz/V, crystal frequency of some discrete value between 13 MHz and 38.4 MHz and proper charge pump current, we get the optimized capacitor value less than 120 pF over loop parameter variations, which is suitable for on chip realization. The overall phase noises are -81 dBc/Hz and -129 dBc/Hz at 1 kHz and 1.45 MHz respectively in simulation for worst case.