DEV: Design explorer for verification

While the design complexity increases, tape-out schedule remains tight hence prompting development of a tool for applications in pre-silicon system to gate-level verification and ASIC design. The tool is developed to mitigate problems such as difficulty in hierarchical path name generation, difficulty in obtaining relation between interconnected blocks with regard to instances, ports, nets, and behavioural statements in a more meaningful way, difficulty in seeing the big picture of a design when the HDL code is extremely long even with the help of the automated tracing feature in third-party proprietary tool, and difficulty in tracing signals in ASIC designs. Data mining concept, arithmetic series and motivation from Google search engine are applied in the development of the tool with Perl and C++ as the programming languages. As a result of incremental development, current prototype of the tool known as Design Explorer for Verification (DEV) is capable of extracting I/O metadata, structural metadata (instances, ports and nets), behavioural metadata, and has a tree diagram (hierarchical graph) generator. The prototype is applied in full-chip RTL/Gate-level Configuration/JTAG verification, hierarchical path name debugging in full-chip verification, and full-chip contention check. The devices involved are Stratix® IV GX and Hardcopy® III.