Post breakdown reliability enhancement of ULSI circuits with novel gate dielectric stacks

Reliability is a key performance indicator of any semiconductor device or circuit fabricated, apart from its other performance parameters such as improved current drive, clocking speed, carrier mobility, fan-in, fan-out, lower power dissipation etc. It is necessary to be able to quantitatively estimate the lifetime of a given circuit based on the accelerated life test data that is usually collected at the transistor (device) level. At the front-end, breakdown of the ultra-thin gate dielectric consists of two stages-(1) time dependent dielectric breakdown (TDDB) and (2) post breakdown (Post-BD). While most reliability studies at the circuit level are confined to the TDDB stage, it is worth noting that the initial durations of the post-BD stage when the gate current shows random telegraph noise (RTN) fluctuations (known as digital breakdown) provide significant reliability lifetime enhancement of the circuit without compromising much on the other circuit performance characteristics. In this study, the electrical characterization and reliability features of the digital breakdown (Di-BD) stage at the ¿device level¿ are first discussed. This is followed by the development of simple statistical tools and Monte Carlo simulation techniques to predict the ULSI post-BD ¿circuit-level¿ reliability enhancement given the device level failure data. The results of this study are of direct relevance to the industry and the technique presented here has the potential to be implemented as a new reliability quantification methodology at the circuit level.