A fast single slope ADC with vernier delay line technique

The paper presents a 9-bit single slope analog to digital converter (ADC) using a two-level vernier delay line (VDL) technique. The amplitude to time conversion architecture is aim to reduce the errors due to comparator delays and input offset. Results indicated that the comparator timing error has been reduced to less than 10 ps and the offset voltage is less than 1%. The time conversion part has the maximum sampling rate of 50Msps and the time resolution of 19.5ps with the differential non-linearity (DNL) within ±0.5 LSB, and the integral non-linearity (INL) within -0.22 and 0.56 LSB. The ADC has a sampling rate of 5 Msps and is realized with the CMOS 0.18um 1P6M technology.