A novel clock feed-through distortion cancellation method for SI-circuits

A novel method that, in theory, cancels all clock feed-through distortion in SI-circuits is presented and verified by simulations. Sensivity of the distortion cancellation is discussed and it is shown to be negligible for other parameters than switch transistor sizes and clock skew. It is demonstrated with a simulation that a significant improvement in linearity can be obtained even after moderate process variations.