A review of dynamic power management methods in NoC under emerging design considerations

A review of dynamic and adaptive techniques for power management of on-chip interconnects, under emerging design considerations, is presented. The progress of IC technology has introduced novel methods, architectures and new challenges for power-aware design exploration. An examination of state-of-the-art power management techniques enables feasible and efficient design of future NoC platforms. This review first analyzes the new challenges, architectures and technologies, including PVT (process, voltage, temperature) variations, rapidly increasing leakage power, multiple on-chip PDN (power delivery network) as well as other architectures, which bring new considerations in low-power design exploration. A wide selection of dynamic power-saving techniques for on-chip interconnects are examined, classified into several categories including run-time datapath configuration, supply configuration and adaptive encoding. The effects and feasibility of these methods, especially their potentials in future technology, are judiciously analyzed. An outlook on generic power management paradigms in next-generation NoCs concludes the review.