A 2–5 Gb/s fully differential 3X oversampling CDR for high-speed serial data link

This paper presents the design and implementation of a fully differential 3X oversampling clock and data recovery (CDR) circuit for high-speed serial data link. The CDR is capable of operating at any speed from 2 to 5 Gb/s. The architecture of the CDR replaces the analog VCO and loop filter used in analog PLL based CDR with digital circuits. The CDR uses a digital threshold decision technique to improve the jitter tolerance performance. System level simulation shows that the CDR has a high frequency jitter tolerance of 0.67 UI and acquisition time of 8 baud period. The CDR is implemented in 65 nm CMOS process technology. The post-layout simulation is performed for 2⁷-1 PRBS data. The CDR consumes 39 mW from 1.1 V power supply at 5 Gb/s. The core CDR circuit occupies an area of 0.013 mm².