Hardware implementation of mapper for faster-than-Nyquist signaling transmitter

This paper presents the implementation of the mapper block in a faster-than-Nyquist (FTN) signaling transmitter. The architecture is look-up table (LUT) based and the complexity is reduced to a few adders and a buffer to store intermediate results. Two flavors of the architecture has been designed and evaluated in this article, one, a register based implementation for the buffer and the other using a random access memory (RAM). The tradeoff between the two is throughput versus area. The register based implementation is fast requiring only one clock cycle to complete the calculation (i.e a read, calculate and write back) for every incoming FTN symbol. However, it becomes prohibitive when systems with large number of sub-carriers (>64) is considered. The RAM based implementation provides a better solution in terms of area with slightly lower throughput. The mapper has been targetted for both FPGA (Xilinx Virtex-II Pro) and ASIC (130 nm standard cell CMOS) implementations. The design has been successfully tested on the FPGA and its output verified with the reference MATLAB model.