Implementation of radio data systems decoder

In this paper, we propose the design method and the structure of a decoder with shortened cyclic code for radio data systems (RDS). Without microprocessor the logic gates are used to implement the hardware of the decoder, moreover, the decoder not only can decode the received message of RDS, but also has the functions of synchronization, error detection and error correction. The proposed decoder includes four function blocks which are serial-to-parallel circuits, group-and-block synchronization detection circuits, decoding-and-correction circuits, and multiplex data parallel output circuits. The whole chip has been measured under the combination with other peripheral components, such as RF tuner, demodulator, microprocessor, and memory, on the board. The operation of the RDS receiver with this chip has also been tested through the transceiver environment setup, and the test results demonstrate that the chip can fully decode the RDS signal in the real word.