A 1.2V 10bit 83MSps pipeline ADC in 130nm CMOS

A 1.2V 10bit 83MS/s pipeline ADC implemented in 130nm CMOS Technology is described. Emphasis was placed on noise analysis and capacitance optimization. Experience of operational amplifier, comparator and switch design were also shared. This design achieves INL and DNL of +0.65/−0.53LSB and +0.33/−0.33LSB respectively, while SNDR is 57.7dB.