A CMOS bootstrapped switch with novel clock feed-through compensation

A new clock feed-through compensation configuration and corresponding bootstrapped switch are presented and designed optimally with UMC Mixed-Mode/RF 0.18 ¿m 1P6M P-Sub Twin-Well CMOS process by orientating and elaborate designing the switch MOSFETs that have influence on the delay path match of the clock boosting circuit. HSPICE simulation results show that the proposed clock feed-through compensation configuration can not only enhance the sampling accuracy under the variations of process, power supply voltage, temperature and capacitors but also decrease even harmonic, high-order odd harmonic and THD on the whole effectively.