An optimized architecture of cascaded crossbar switches in SoC systems

For high frequency design of SoC systems, cascaded crossbar switches become more and more popular. In this paper, we present a method based on FFT-butterfly architecture. This method can provide optimal topology of cascaded crossbar switches, which consists of multiple small crossbar switches. We apply it to AMBA3 AXI-based bus system design. Experimental results show that the proposed methods allow SoC designs with higher performance, with a reduction to area by 16.6%.