Time evolution of the voltage-controlled signal in charge pump PLL applications

A transient analysis of the acquisition processes in the loop filter of a frequency synthesizer is presented. A concise mathematical model for the voltage control signal used to tune a voltage controlled oscillator is derived for the transient lock-in process. A frequency synthesizer implemented in a 0.13 ¿m CMOS technology is used to demonstrate the theoretical analysis. For the particular case examined in this paper, the calculated, simulated, and measured transient signal values differed from each other by less than 7% over the lock-in time interval.