All-digital phase-locked loop with an adaptive bandwidth design procedure

A design method of a second-order adaptive-bandwidth all-digital phase-locked loop (ADB-ADPLL) is developed. Based on a discrete-time analogy of a continuous-time PLL (CTPLL) with the z-transform, the design criterion of the ADB-ADPLL is derived. With an ADB-ADPLL, the loop bandwidth and lock-in time are balanced. According to the design criterion, the ratio of the loop noise bandwidth to the reference input frequency will be a constant if the sampling frequency is maintained as a fixed multiplier of the input reference frequency. A design example of the ADB-ADPLL is illustrated, where simulation results are presented for a performance demonstration.