Design and simulation study for stacked IC packages with spacer structure

Most future electronic applications require better reliability and performance as well as lower-priced productions. In order to reach these general demands, three-dimensional (3D) IC packaging technologies are assuming important roles and have been vastly studied in electronic industry. In this investigation, two kinds of designs of experiments (DOE) analysis by wedding finite element analysis (FEA) are carried out to realize effects of material properties of spacers and geometry of stacked IC packages. Through the results, most desirable values of spacers' material properties and significant geometrical factors in stacked IC packages can be obtained. The simulated results can be most effectively used when optimum stress solutions in stacked IC packages with spacer structure are needed.