A novel high performance substrate and the processes thereof

This paper introduces a novel high performance substrate for digital and RF application. Instead of line width, we indicated that the size of VIA land is the key issue to improve routing density. In a practical example, if the VIA land can be reduced to 30 um, with 15/15 um line/space width, a bump grid array which has 3 rows and 105 um pitch can be easily fanned out by just one layer. For the target of high routing density, we develop a novel process and successfully meet the aforesaid criteria. Accordingly, the design of flip chip substrates become easy and the cost of advanced packaging can be reduced.