A Design and Implementation of High-Speed 3DES Algorithm System

This paper introduces the principle of 3DES encryption algorithm and the detailed description of the algorithm design and implementation on FPGA. For the improvement of the S-box, it uses a single S-box to replace the original eight S-boxes. This will not only greatly reduces the size of circuit but also reduces the power consumption of the entire circuit. In the design, pipelining technology is used to improve its running speed. All the modules are using Verilog HDL hardware description language to achieve, and at last it is downloaded to the FPGA chip.